Field of the Invention
This invention is in the field of serial peripheral interface (SPI) busses, and related serial communications methods used for short distance communication between embedded system devices.
Description of the Related Art
The serial peripheral interface (SPI) bus is a popular embedded system interface, often used for communications between a “master” device, such as a microprocessor or microcontroller (here called a processor), and various “slave” system peripherals.
In the standard SPI bus scheme, a master device controls the timing of clock pulses (often designated as SCLK, SCK or CLK for “serial clock”) using a SCLK port. The various master clock pulses output from the SCLK port are transmitted, via appropriate wires, to the SCLK/CLK ports of one or more various SPI slave peripheral devices. These clock pulses are used to synchronize communications between the master device and various SPI slave peripherals. One master SLCK port can be connected over a SCLK/CLK wire to many different SPI slave peripheral SCLK/CLK ports, so that they are all time synchronized.
The master device typically uses another serial port, often designated the MOSI port (for master output save input), to transmit serial data, in the form of time sequential binary 1 and 0 signals, over a MOSI wire to the various slave peripherals. The different slave peripherals are often all connected to the same MOSI wire via their respective single MOSI ports. The master device transmits serially transmits data, on a one bit per clock pulse basis, in the form of binary 1 and 0 signals.
In the standard SPI bus scheme, one MOSI wire may connect to all of the slave peripherals, and thus each slave peripheral may see the same series of bits. Thus in this configuration a single standard MOSI port or output acts like a “party line”, talking to a plurality of different slave SPI peripheral devices.
To allow a SPI master device to send (and receive) data only from certain selected SPI slave peripheral devices, a SPI master device can send “slave select” or “chip select” (called SS or CS) signals to a corresponding SS/CS port on the various slave SPI peripheral devices. When a particular SPI slave peripheral device receives a chip select signal on its (usually one) SS/CS port, that particular slave select peripheral knows that it should receive data via its MOSI and (SCLK) ports. In the absent of the appropriate chip select signal, the slave SPI peripheral device will ignore data signals from its particular MOSI port.
To send SS/CS chip select signals, the SPI master device can either use a dedicated SPI SS/CS port, or alternatively use other ports, such as general purpose input output ports (GPIO) ports.
To allow various slave peripherals to transmit data back to the master device, the various slave peripherals often have a master input slave output (MISO) port configured to transmit serial binary data back to the master device's MISO port via a MISO wire. The rate of data transmission on the MISO port is also controlled by the SPI mater device's SLCK/CLK pulses. The standard SPI MISO port also operates on a “party line” basis, where one SPI master device MISO port may be connected to a various MISO ports on various slave SPI peripheral devices. Chip select commands are also used to determine which slave SPI device can transmit at any given time, and typically a SPI slave peripheral device will only transmit data back to the SPI master device when that particular slave device has been selected via its SS/CS port.
Typically the master device will send (or receive) data from the various slave devices in groups of 8 bit words (e.g. n×8 bits, where n can be 1 or greater). However other word sizes (12 bit words, 32 bit words, etc.) may also be used.
After the SPI bus/interface was introduced, an extension of this interface, called the Quad serial peripheral interface (Quad-SPI, or QSPI), was introduced. The QSPI interface is often designed to be backward compatible with the earlier SPI interface, but the QSPI interface also adds additional functionality. In particular, the QSPI interface is oriented towards transmitting or receiving data at a much faster rate of a nibble (e.g. 4-bits) per SCLK/CLK clock pulse, rather than the 1-bit per SCLK/CLK rate of the earlier SPI bus/interface. Most recently, an Octal-SPI bus/interface has also been introduced, which, while backward compatible with the SPI and QSPI interface, can transmit data at the still faster rate of a byte (e.g. 8-bits) per SCLK/CLK clock cycle. For conciseness, however, we will generally use the term QSPI to denote either the QSPI or Octal-SPI bus/interface.
QSPI interface generalizes the SPI interface's 1 bit wide MOSI port and 1 bit wide MISO into four input/output ports that can be configured so that all four ports can either all simultaneously transmit data during a given operation, or all four ports can simultaneously receive data during a given operation. Here, at least when configured so that all four master device input/output ports are configured to transmit data, these four ports will be referred to as the QSPI data outputs. These four ports are often numbered as IO0, IO1, IO2, IO3, or alternatively as QSPI0, QSPI1, QSPI2, and QSPI3 ports.
The QSPI interface is most commonly used to allow QSPI equipped processors to send and receive data from QSPI interface equipped memory type slave peripherals, such as flash memory chips, and the like. Because they are sending data at a rate of a nibble (4-bits) per SPI clock pulse, rather than at the slower SPI 1-bit per SPI clock pulse, such QSPI peripherals and devices can thus send and receive four times as much data per SCLK clock pulse as earlier SPI interfaces. Because the QSPI interface has been designed to be backward compatible with the SPI interface, such QSPI interfaces can also be used to send and receive data from standard SPI equipped devices and peripherals as well.
A simple introduction to these various concepts can be found in the Wikipedia Serial Peripheral Interface Bus article provided by Wikipedia (as of Apr. 5, 2017) at en.wikipedia.org/wiki/Serial_Peripheral_interface_Bus, and by the SPI Bus Tutorial white paper provided by Corelis.com, www.corelis.com/whitepapers/BusPro-S_SPI_Tutorial.pdf. Both have been provided as non-patent literature for this application.
Frequency Synthesizers:
Frequency synthesizers, described by Chenakin, U.S. patent application Ser. No. 15/469,434, the entire contents of which are incorporated by reference, are electronic systems that translate input signals at a first frequency into output signals at a second (and typically higher) frequency.
Such frequency synthesizers can often produce output signals in the Gigahertz frequency region or higher. Frequency synthesizers can be viewed as being an example of a type of embedded system where a master processor device often communicates with various system peripherals such as phase locked loops, voltage controlled oscillators, mixers, phase shifters, frequency dividers, synthesizers, and the like. At least some of these various components can be implemented as, or controlled by, various SPI equipped peripherals.
Additional background on frequency synthesizers can be found in Chenakin, “Frequency Synthesis: Current Solutions and New Trends”, Microwave Journal, May 2007, pages 256-266; and Chenakin “Building a Microwave Frequency Synthesizer—Part 1: Getting Started” in High Frequency Electronics, May 2008, pages 58-67.